ra8_systick.c

Go to the documentation of this file.

 
#include "ra8_systick.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_log.h"

static const char* const s_tag = "ra8_systick";

typedef enum : uintptr_t {
  k_ra8_systick_csr = 0xE000E010UL, 
  k_ra8_systick_rvr = 0xE000E014UL, 
  k_ra8_systick_cvr = 0xE000E018UL, 
  k_ra8_dwt_demcr   = 0xE000EDFCUL, 
  k_ra8_dwt_ctrl    = 0xE0001000UL, 
  k_ra8_dwt_cyccnt  = 0xE0001004UL, 
} ra8_systick_reg_addr_t;

typedef enum : uint32_t {
  k_ra8_systick_csr_enable    = 0x00000001UL, 
  k_ra8_systick_csr_tickint   = 0x00000002UL, 
  k_ra8_systick_csr_clksource = 0x00000004UL, 
  k_ra8_dwt_demcr_trcena      = 0x01000000UL, 
  k_ra8_dwt_ctrl_cyccntena    = 0x00000001UL, 
} ra8_systick_bit_t;

RA8_HW_REGISTER_ACCESS RA8_INTERNAL static inline volatile uint32_t*
internal_systick_reg(ra8_systick_reg_addr_t addr)
{
  return (volatile uint32_t*)addr;
}
 
ra8_err_t ra8_systick_reload_for(uint32_t cpu_hz, uint32_t tick_hz, uint32_t* out_reload)
{
  RA8_CHECK_NULL_PTR(out_reload, s_tag, "out_reload is NULL");
 
  /* Reject a zero clock or a zero tick rate: both make the reload arithmetic
   * meaningless (a 0 Hz core, or a division by zero). */
  if ((cpu_hz == 0U) || (tick_hz == 0U)) {
    ra8_log_error(s_tag, "cpu_hz / tick_hz must be non-zero");
    return k_ra8_err_invalid_arg;
  }
 
  const uint32_t ticks = cpu_hz / tick_hz;
  if (ticks == 0U) {
    /* Clock slower than one tick period -> reload would underflow. */
    ra8_log_error(s_tag, "cpu_hz below one tick period");
    return k_ra8_err_invalid_arg;
  }
 
  const uint32_t reload = ticks - 1U;
  if (reload > (uint32_t)k_ra8_systick_rvr_max) {
    /* Too high for the 24-bit SYST_RVR field: refuse rather than truncate,
     * which would silently make the tick far too fast. */
    ra8_log_error(s_tag, "reload exceeds 24-bit SysTick range");
    return k_ra8_err_out_of_range;
  }
 
  *out_reload = reload;
  return k_ra8_ok;
}
 
ra8_err_t ra8_systick_configure(uint32_t reload, ra8_systick_clock_source_t src, bool tick_irq)
{
  if (reload > (uint32_t)k_ra8_systick_rvr_max) {
    ra8_log_error(s_tag, "reload exceeds 24-bit SysTick range");
    return k_ra8_err_out_of_range;
  }
 
  /* Arm v8-M ARM: SYST_CSR -- clear ENABLE first so the reload/current writes
   * land on a stopped counter, then re-enable with the requested config. */
  *internal_systick_reg(k_ra8_systick_csr) = 0U;
  *internal_systick_reg(k_ra8_systick_rvr) = reload;
  *internal_systick_reg(k_ra8_systick_cvr) = 0U;
 
  uint32_t csr_val = (uint32_t)k_ra8_systick_csr_enable;
  if (tick_irq) {
    csr_val |= (uint32_t)k_ra8_systick_csr_tickint;
  }
  if (src == k_ra8_systick_clk_cpu) {
    csr_val |= (uint32_t)k_ra8_systick_csr_clksource;
  }
  *internal_systick_reg(k_ra8_systick_csr) = csr_val;
  return k_ra8_ok;
}
 
ra8_err_t ra8_systick_set_reload(uint32_t reload)
{
  if (reload > (uint32_t)k_ra8_systick_rvr_max) {
    ra8_log_error(s_tag, "reload exceeds 24-bit SysTick range");
    return k_ra8_err_out_of_range;
  }
 
  /* Arm v8-M ARM: re-arm the reload, then any write to SYST_CVR clears it so
   * the next count starts from the new reload. The SYST_CSR control bits are
   * deliberately left as-is. */
  *internal_systick_reg(k_ra8_systick_rvr) = reload;
  *internal_systick_reg(k_ra8_systick_cvr) = 0U;
  return k_ra8_ok;
}
 
uint32_t ra8_systick_current_value(void)
{
  /* Arm v8-M ARM: SYST_CVR -- reading it is side-effect free (only a write
   * clears the counter). */
  return *internal_systick_reg(k_ra8_systick_cvr);
}
 
void ra8_dwt_cyccnt_enable(void)
{
  /* Arm v8-M ARM: DEMCR.TRCENA unlocks the DWT unit; DWT_CTRL.CYCCNTENA then
   * starts DWT_CYCCNT. Read-modify-write preserves any other trace bits. */
  *internal_systick_reg(k_ra8_dwt_demcr) |= (uint32_t)k_ra8_dwt_demcr_trcena;
  *internal_systick_reg(k_ra8_dwt_ctrl) |= (uint32_t)k_ra8_dwt_ctrl_cyccntena;
}
 
void ra8_dwt_cyccnt_reset(void)
{
  /* Arm v8-M ARM: DWT_CYCCNT is writable; zero it to start a measured window.
   */
  *internal_systick_reg(k_ra8_dwt_cyccnt) = 0U;
}
 
uint32_t ra8_dwt_cyccnt_read(void)
{
  /* Arm v8-M ARM: DWT_CYCCNT free-running cycle counter, read side-effect free.
   */
  return *internal_systick_reg(k_ra8_dwt_cyccnt);
}