ra8_scb.c

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#include "ra8_scb.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"

typedef enum : uintptr_t {
  k_ra8_scb_vtor  = 0xE000ED08UL, 
  k_ra8_scb_cfsr  = 0xE000ED28UL, 
  k_ra8_scb_hfsr  = 0xE000ED2CUL, 
  k_ra8_scb_dfsr  = 0xE000ED30UL, 
  k_ra8_scb_mmfar = 0xE000ED34UL, 
  k_ra8_scb_bfar  = 0xE000ED38UL, 
  k_ra8_scb_afsr  = 0xE000ED3CUL, 
  k_ra8_scb_sfsr  = 0xE000EDE4UL, 
  k_ra8_scb_sfar  = 0xE000EDE8UL, 
  k_ra8_scb_demcr = 0xE000EDFCUL, 
} ra8_scb_reg_addr_t;

typedef enum : uint32_t {
  k_ra8_scb_demcr_trcena = 0x01000000UL, 
} ra8_scb_bits_t;

RA8_HW_REGISTER_ACCESS RA8_INTERNAL static inline volatile uint32_t*
internal_scb_reg(ra8_scb_reg_addr_t addr)
{
  return (volatile uint32_t*)addr;
}
 
ra8_err_t ra8_scb_read_fault_status(ra8_scb_fault_status_t* out)
{
  static const char* const tag = "ra8_scb";
 
  RA8_CHECK_NULL_PTR(out, tag, "read_fault_status: out");
  /* Arm v8-M ARM B3.2 "System Control Block": configurable / hard / debug
   * fault status, then the MemManage / BusFault / Auxiliary registers. Plain
   * reads -- no side effect, nothing is cleared. */
  out->cfsr  = *internal_scb_reg(k_ra8_scb_cfsr);
  out->hfsr  = *internal_scb_reg(k_ra8_scb_hfsr);
  out->dfsr  = *internal_scb_reg(k_ra8_scb_dfsr);
  out->mmfar = *internal_scb_reg(k_ra8_scb_mmfar);
  out->bfar  = *internal_scb_reg(k_ra8_scb_bfar);
  out->afsr  = *internal_scb_reg(k_ra8_scb_afsr);
  /* Arm v8-M ARM (Security Extension): SFSR / SFAR are banked to the Secure
   * state. Read from Secure they carry the real cause / address; read from
   * Non-secure they are RAZ -- never a fault -- so this is safe in either
   * world without a guard. */
  out->sfsr = *internal_scb_reg(k_ra8_scb_sfsr);
  out->sfar = *internal_scb_reg(k_ra8_scb_sfar);
  return k_ra8_ok;
}
 
void ra8_scb_set_vtor(uintptr_t base)
{
  /* Arm v8-M ARM B3.2.2 "VTOR, Vector Table Offset Register": point the core
   * at a new vector-table base. Hardware ignores the low alignment bits. */
  *internal_scb_reg(k_ra8_scb_vtor) = (uint32_t)base;
}
 
uintptr_t ra8_scb_get_vtor(void)
{
  /* Arm v8-M ARM B3.2.2 "VTOR": current vector-table base address. */
  return (uintptr_t)*internal_scb_reg(k_ra8_scb_vtor);
}
 
bool ra8_scb_trace_enabled(void)
{
  /* Arm v8-M ARM (Debug) DEMCR.TRCENA (bit 24): trace subsystem power. */
  const uint32_t demcr = *internal_scb_reg(k_ra8_scb_demcr);
  return (demcr & (uint32_t)k_ra8_scb_demcr_trcena) != 0U;
}
 
void ra8_scb_trace_enable(void)
{
  /* Arm v8-M ARM (Debug) DEMCR.TRCENA (bit 24): set it, preserving every
   * other bit -- a read-modify-write, not a blind store. */
  const uint32_t demcr               = *internal_scb_reg(k_ra8_scb_demcr);
  *internal_scb_reg(k_ra8_scb_demcr) = demcr | (uint32_t)k_ra8_scb_demcr_trcena;
}