ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_ov5640.c
Go to the documentation of this file.
1
18
19#include "ra8_ov5640.h"
20
21#include <stdint.h>
22
23#include "ra8_attributes.h"
24#include "ra8_check.h"
25#include "ra8_err.h"
26
27/* =============================================================================
28 * OV5640 constants (typed enums -- no magic numbers)
29 * =============================================================================
30 */
31
33typedef enum : uint16_t {
86
88typedef enum : uint8_t {
141
148
156
163typedef struct {
164 uint16_t reg;
165 uint8_t val;
167
169typedef struct {
170 uint16_t reg;
171 uint8_t mask;
172 uint8_t value;
174
176typedef struct {
177 uint8_t length_hi;
178 uint8_t length_mid;
179 uint8_t length_lo;
180 uint8_t overflow;
181 uint8_t jpeg_input;
182 uint8_t jpeg_ctrl01;
183 uint8_t jpeg_header;
184 uint8_t vfifo_ctrl00;
185 uint8_t width_hi;
186 uint8_t width_lo;
187 uint8_t height_hi;
188 uint8_t height_lo;
189 uint8_t href_minimum;
192
202 /* ---- clock / PLL: sysclk from PLL fed by the 24 MHz XVCLK ---- */
203 {0x3103, 0x11},
204 {0x4740, 0x20},
205 {0x4050, 0x6E},
206 {0x4051, 0x8F},
207 {0x3103, 0x02},
208 {0x3017, 0x7F},
209 {0x3018, 0xFF},
210 {0x302C, 0xC2},
216 {0x3630, 0x2E},
217 {0x3631, 0x0E},
218 {0x3632, 0xE2},
219 {0x3633, 0x23},
220 {0x3621, 0xE0},
221 {0x3704, 0xA0},
222 {0x3703, 0x5A},
223 {0x3715, 0x78},
224 {0x3717, 0x01},
225 {0x370B, 0x60},
226 {0x3705, 0x1A},
227 {0x3905, 0x02},
228 {0x3906, 0x10},
229 {0x3901, 0x0A},
230 {0x3731, 0x12},
231 {0x3600, 0x08},
232 {0x3601, 0x33},
233 {0x302D, 0x60},
234 {0x3620, 0x52},
235 {0x371B, 0x20},
236 {0x471C, 0x50},
237 {0x3A13, 0x43},
238 {0x3A18, 0x00},
239 {0x3A19, 0xF8},
240 {0x3635, 0x1C},
241 {0x3636, 0x03},
242 {0x3634, 0x40},
243 {0x3622, 0x01},
244 /* ---- live-scene exposure, anti-flicker, and black-level controls ---- */
245 {0x3C01, 0xB4},
246 {0x3C04, 0x28},
247 {0x3C05, 0x98},
248 {0x3C06, 0x00},
249 {0x3C07, 0x08},
250 {0x3C08, 0x00},
251 {0x3C09, 0x1C},
252 {0x3C0A, 0x9C},
253 {0x3C0B, 0x40},
254 {0x3618, 0x00},
255 {0x3612, 0x29},
256 {0x3708, 0x64},
257 {0x3709, 0x52},
258 {0x370C, 0x03},
259 {0x3A00, 0x3C},
260 {0x3A02, 0x05},
261 {0x3A03, 0xC4},
262 {0x3A08, 0x00},
263 {0x3A09, 0x93},
264 {0x3A0A, 0x00},
265 {0x3A0B, 0x7B},
266 {0x3A0D, 0x08},
267 {0x3A0E, 0x06},
268 {0x3A0F, 0x30},
269 {0x3A10, 0x28},
270 {0x3A11, 0x60},
271 {0x3A14, 0x05},
272 {0x3A15, 0xC4},
273 {0x3A1B, 0x30},
274 {0x3A1E, 0x26},
275 {0x3A1F, 0x14},
276 {0x3503, 0x00},
277 {0x3C00, 0x04},
278 {0x4001, 0x02},
279 {0x4004, 0x02},
280 /* ---- timing: full array windowed to a VGA DVP output ---- */
281 {0x3808, 0x02},
282 {0x3809, 0x80},
283 {0x380A, 0x01},
284 {0x380B, 0xE0},
285 {0x380C, 0x0C},
286 {0x380D, 0x80},
287 {0x380E, 0x07},
288 {0x380F, 0xD0},
289 {0x3800, 0x00},
290 {0x3801, 0x00},
291 {0x3802, 0x00},
292 {0x3803, 0x04},
293 {0x3804, 0x0A},
294 {0x3805, 0x3F},
295 {0x3806, 0x07},
296 {0x3807, 0x9B},
297 {0x3810, 0x00},
298 {0x3811, 0x10},
299 {0x3812, 0x00},
300 {0x3813, 0x06},
301 {0x3814, 0x31},
302 {0x3815, 0x31},
303 {0x3820, 0x41},
304 {0x3821, 0x01},
305 /* ---- ISP + DVP output format: YUV422 (YUYV) ---- */
306 {0x4300, 0x30},
307 {0x501F, 0x00},
308 {0x4713, 0x03},
309 {0x4407, 0x04},
310 {0x460B, 0x35},
311 {0x460C, 0x22},
312 {0x4837, 0x0A},
314 {0x5000, 0xA7},
315 {0x5001, 0xA3},
316 /* ---- ISP scene processing: AWB + colour matrix ---- */
317 {0x5180, 0xFF},
318 {0x5181, 0xF2},
319 {0x5182, 0x00},
320 {0x5183, 0x14},
321 {0x5184, 0x25},
322 {0x5185, 0x24},
323 {0x5186, 0x09},
324 {0x5187, 0x09},
325 {0x5188, 0x09},
326 {0x5189, 0x88},
327 {0x518A, 0x54},
328 {0x518B, 0xEE},
329 {0x518C, 0xB2},
330 {0x518D, 0x50},
331 {0x518E, 0x34},
332 {0x518F, 0x6B},
333 {0x5190, 0x46},
334 {0x5191, 0xF8},
335 {0x5192, 0x04},
336 {0x5193, 0x70},
337 {0x5194, 0xF0},
338 {0x5195, 0xF0},
339 {0x5196, 0x03},
340 {0x5197, 0x01},
341 {0x5198, 0x04},
342 {0x5199, 0x6C},
343 {0x519A, 0x04},
344 {0x519B, 0x00},
345 {0x519C, 0x09},
346 {0x519D, 0x2B},
347 {0x519E, 0x38},
348 {0x5381, 0x1E},
349 {0x5382, 0x5B},
350 {0x5383, 0x08},
351 {0x5384, 0x0A},
352 {0x5385, 0x7E},
353 {0x5386, 0x88},
354 {0x5387, 0x7C},
355 {0x5388, 0x6C},
356 {0x5389, 0x10},
357 {0x538A, 0x01},
358 {0x538B, 0x98},
359 /* ---- ISP sharpening, gamma, saturation, and lens shading ---- */
360 {0x5300, 0x08},
361 {0x5301, 0x30},
362 {0x5302, 0x10},
363 {0x5303, 0x00},
364 {0x5304, 0x08},
365 {0x5305, 0x30},
366 {0x5306, 0x08},
367 {0x5307, 0x16},
368 {0x5309, 0x08},
369 {0x530A, 0x30},
370 {0x530B, 0x04},
371 {0x530C, 0x06},
372 {0x5480, 0x01},
373 {0x5481, 0x08},
374 {0x5482, 0x14},
375 {0x5483, 0x28},
376 {0x5484, 0x51},
377 {0x5485, 0x65},
378 {0x5486, 0x71},
379 {0x5487, 0x7D},
380 {0x5488, 0x87},
381 {0x5489, 0x91},
382 {0x548A, 0x9A},
383 {0x548B, 0xAA},
384 {0x548C, 0xB8},
385 {0x548D, 0xCD},
386 {0x548E, 0xDD},
387 {0x548F, 0xEA},
388 {0x5490, 0x1D},
389 {0x5580, 0x02},
390 {0x5583, 0x40},
391 {0x5584, 0x10},
392 {0x5589, 0x10},
393 {0x558A, 0x00},
394 {0x558B, 0xF8},
395 {0x5800, 0x23},
396 {0x5801, 0x14},
397 {0x5802, 0x0F},
398 {0x5803, 0x0F},
399 {0x5804, 0x12},
400 {0x5805, 0x26},
401 {0x5806, 0x0C},
402 {0x5807, 0x08},
403 {0x5808, 0x05},
404 {0x5809, 0x05},
405 {0x580A, 0x08},
406 {0x580B, 0x0D},
407 {0x580C, 0x08},
408 {0x580D, 0x03},
409 {0x580E, 0x00},
410 {0x580F, 0x00},
411 {0x5810, 0x03},
412 {0x5811, 0x09},
413 {0x5812, 0x07},
414 {0x5813, 0x03},
415 {0x5814, 0x00},
416 {0x5815, 0x01},
417 {0x5816, 0x03},
418 {0x5817, 0x08},
419 {0x5818, 0x0D},
420 {0x5819, 0x08},
421 {0x581A, 0x05},
422 {0x581B, 0x06},
423 {0x581C, 0x08},
424 {0x581D, 0x0E},
425 {0x581E, 0x29},
426 {0x581F, 0x17},
427 {0x5820, 0x11},
428 {0x5821, 0x11},
429 {0x5822, 0x15},
430 {0x5823, 0x28},
431 {0x5824, 0x46},
432 {0x5825, 0x26},
433 {0x5826, 0x08},
434 {0x5827, 0x26},
435 {0x5828, 0x64},
436 {0x5829, 0x26},
437 {0x582A, 0x24},
438 {0x582B, 0x22},
439 {0x582C, 0x24},
440 {0x582D, 0x24},
441 {0x582E, 0x06},
442 {0x582F, 0x22},
443 {0x5830, 0x40},
444 {0x5831, 0x42},
445 {0x5832, 0x24},
446 {0x5833, 0x26},
447 {0x5834, 0x24},
448 {0x5835, 0x22},
449 {0x5836, 0x22},
450 {0x5837, 0x26},
451 {0x5838, 0x44},
452 {0x5839, 0x24},
453 {0x583A, 0x26},
454 {0x583B, 0x28},
455 {0x583C, 0x42},
456 {0x583D, 0xCE},
457 {0x5025, 0x00},
458 /* ---- DVP pads, interface control, and sync polarity ---- */
459 {0x3000, 0x20},
460 {0x3002, 0x1C},
461 {0x3004, 0xFF},
462 {0x3006, 0xC3},
463 {0x300E, 0x58},
464 {0x302E, 0x00},
465 {0x440E, 0x00},
466 {0x4709, 0x02},
467 {0x470A, 0x00},
468 {0x470B, 0x00},
469 {0x471D, 0x00},
470 {0x4713, 0x03},
471 {0x471C, 0x50},
472 {0x4740, 0x20},
473 {0x4005, 0x1A},
474 {0x3406, 0x00},
475 {0x3503, 0x00},
476 {0x3008, 0x02},
477 {0x4745, 0x00},
478 {0x4301, 0x01},
479 /* ---- ISP test pattern disabled: stream the lens image ---- */
480 {0x503D, 0x00},
481};
482
483/* See the public header for the documented contract. */
485{
486 RA8_CHECK_NULL_PTR(dev, "ov5640", "init");
487 RA8_CHECK_NULL_PTR(bus, "ov5640", "init");
488 RA8_CHECK_NULL_PTR(bus->read_reg, "ov5640", "init");
489 RA8_CHECK_NULL_PTR(bus->write_reg, "ov5640", "init");
490 RA8_CHECK_NULL_PTR(bus->delay_ms, "ov5640", "init");
491 *dev = (ra8_ov5640_t){
492 .bus = *bus,
493 .address = (uint8_t)k_ra8_ov5640_addr_primary,
494 .initialized = true,
495 };
496 return k_ra8_ok;
497}
498
499/* See the public header for the documented contract. */
500ra8_err_t ra8_ov5640_read_reg(ra8_ov5640_t* dev, uint16_t reg, uint8_t* out_value)
501{
502 RA8_CHECK_NULL_PTR(dev, "ov5640", "read");
503 RA8_CHECK_NULL_PTR(out_value, "ov5640", "read");
504 if (!dev->initialized) {
506 }
507 return dev->bus.read_reg(dev->bus.ctx, dev->address, reg, out_value);
508}
509
510/* See the public header for the documented contract. */
511ra8_err_t ra8_ov5640_write_reg(ra8_ov5640_t* dev, uint16_t reg, uint8_t value)
512{
513 RA8_CHECK_NULL_PTR(dev, "ov5640", "write");
514 if (!dev->initialized) {
516 }
517 return dev->bus.write_reg(dev->bus.ctx, dev->address, reg, value);
518}
519
538internal_ov5640_update_bits(ra8_ov5640_t* dev, uint16_t reg, uint8_t mask, uint8_t value)
539{
540 uint8_t current = 0U;
541 ra8_err_t err = ra8_ov5640_read_reg(dev, reg, &current);
542 if (err != k_ra8_ok) {
543 return err;
544 }
545 const uint8_t updated = (uint8_t)((current & (uint8_t)~mask) | (value & mask));
546 return ra8_ov5640_write_reg(dev, reg, updated);
547}
548
567internal_ov5640_verify(ra8_ov5640_t* dev, const ra8_ov5640_reg_expect_t* expected, uint32_t count)
568{
569 for (uint32_t i = 0U; i < count; i += 1U) {
570 uint8_t actual = 0U;
571 ra8_err_t err = ra8_ov5640_read_reg(dev, expected[i].reg, &actual);
572 if (err != k_ra8_ok) {
573 return err;
574 }
575 if ((actual & expected[i].mask) != expected[i].value) {
577 }
578 }
579 return k_ra8_ok;
580}
581
598{
599 uint8_t hi = 0U;
600 uint8_t lo = 0U;
601 ra8_err_t err = ra8_ov5640_read_reg(dev, (uint16_t)k_ov5640_reg_chip_id_hi, &hi);
602 if (err == k_ra8_ok) {
603 err = ra8_ov5640_read_reg(dev, (uint16_t)k_ov5640_reg_chip_id_lo, &lo);
604 }
605 if (err == k_ra8_ok) {
606 *out_id = (uint16_t)(((uint16_t)hi << (uint16_t)k_ov5640_hi_byte_shift) | (uint16_t)lo);
607 }
608 return err;
609}
610
611/* See the public header for the documented contract. */
613{
614 RA8_CHECK_NULL_PTR(dev, "ov5640", "probe");
615 RA8_CHECK_NULL_PTR(out_id, "ov5640", "probe");
616 if (!dev->initialized) {
618 }
619 *out_id = 0U;
620 const uint8_t addrs[2] = {(uint8_t)k_ra8_ov5640_addr_primary,
622 for (uint32_t i = 0U; i < (uint32_t)sizeof(addrs); i++) {
623 dev->address = addrs[i];
624 uint16_t id = 0U;
625 if ((internal_ov5640_read_chip_id(dev, &id) == k_ra8_ok) &&
626 (id == (uint16_t)k_ra8_ov5640_chip_id)) {
627 *out_id = id;
628 return k_ra8_ok;
629 }
630 *out_id = id;
631 }
632 dev->address = (uint8_t)k_ra8_ov5640_addr_primary;
633 return k_ra8_err_not_found;
634}
635
652{
653 const uint32_t count = (uint32_t)(sizeof(s_ov5640_vga_uyvy) / sizeof(ra8_ov5640_reg_write_t));
654 for (uint32_t i = 0U; i < count; i += 1U) {
655 const ra8_err_t err =
657 if (err != k_ra8_ok) {
658 return err;
659 }
660 if (s_ov5640_vga_uyvy[i].reg == (uint16_t)k_ov5640_reg_system_reset00) {
661 dev->bus.delay_ms(dev->bus.ctx, (uint32_t)k_ov5640_mcu_reset_ms);
662 }
663 }
664 return k_ra8_ok;
665}
666
683{
684 static const ra8_ov5640_reg_write_t jpeg_writes[] = {
687 {(uint16_t)k_ov5640_reg_format, (uint8_t)k_ov5640_format_yuyv},
688 {(uint16_t)k_ov5640_reg_isp_mux, (uint8_t)k_ov5640_isp_mux_yuv},
689 };
690 const uint32_t count = (uint32_t)(sizeof(jpeg_writes) / sizeof(ra8_ov5640_reg_write_t));
691 for (uint32_t i = 0U; i < count; i += 1U) {
692 const ra8_err_t err = ra8_ov5640_write_reg(dev, jpeg_writes[i].reg, jpeg_writes[i].val);
693 if (err != k_ra8_ok) {
694 return err;
695 }
696 }
701 if (err == k_ra8_ok) {
706 }
707 if (err == k_ra8_ok) {
711 0U);
712 }
713 if (err == k_ra8_ok) {
717 (uint8_t)k_ov5640_jpeg_clock_mask);
718 }
719 if (err == k_ra8_ok) {
720 err = ra8_ov5640_write_reg(dev,
722 (uint8_t)k_ov5640_mcu_reset_hold);
723 }
724 return err;
725}
726
743{
744 static const ra8_ov5640_reg_expect_t expected[] = {
745 {(uint16_t)k_ov5640_reg_format, (uint8_t)k_ov5640_byte_mask, (uint8_t)k_ov5640_format_yuyv},
746 {(uint16_t)k_ov5640_reg_isp_mux, (uint8_t)k_ov5640_byte_mask, (uint8_t)k_ov5640_isp_mux_yuv},
747 {(uint16_t)k_ov5640_reg_test, (uint8_t)k_ov5640_byte_mask, 0x00U},
748 };
749 return internal_ov5640_verify(dev,
750 expected,
751 (uint32_t)(sizeof(expected) / sizeof(ra8_ov5640_reg_expect_t)));
752}
753
770{
771 static const ra8_ov5640_reg_expect_t expected[] = {
772 {(uint16_t)k_ov5640_reg_system_reset02, (uint8_t)k_ov5640_jpeg_reset_mask, 0x00U},
775 (uint8_t)k_ov5640_jpeg_clock_mask},
779 {(uint16_t)k_ov5640_reg_jpeg_quality,
782 {(uint16_t)k_ov5640_reg_jpeg_mode,
784 (uint8_t)k_ov5640_jpeg_mode_dvp_2},
788 {(uint16_t)k_ov5640_reg_pll_bypass,
789 (uint8_t)k_ov5640_byte_mask,
791 {(uint16_t)k_ov5640_reg_pclk_divider,
792 (uint8_t)k_ov5640_byte_mask,
794 };
795 return internal_ov5640_verify(dev,
796 expected,
797 (uint32_t)(sizeof(expected) / sizeof(ra8_ov5640_reg_expect_t)));
798}
799
800/* See the public header for the documented contract. */
802{
803 RA8_CHECK_NULL_PTR(dev, "ov5640", "configure");
804 if (!dev->initialized) {
806 }
807 if ((mode != k_ra8_ov5640_mode_vga_uyvy) && (mode != k_ra8_ov5640_mode_vga_jpeg)) {
809 }
810 dev->bus.delay_ms(dev->bus.ctx, (uint32_t)k_ov5640_reset_guard_ms);
811 ra8_err_t err =
813 if (err != k_ra8_ok) {
814 return err;
815 }
816 dev->bus.delay_ms(dev->bus.ctx, (uint32_t)k_ov5640_reset_guard_ms);
818 if (mode == k_ra8_ov5640_mode_vga_jpeg) {
820 }
821 if (err != k_ra8_ok) {
822 return err;
823 }
824 dev->bus.delay_ms(dev->bus.ctx, (uint32_t)k_ov5640_cfg_settle_ms);
826 if ((err != k_ra8_ok) || (mode != k_ra8_ov5640_mode_vga_jpeg)) {
827 return err;
828 }
829 return internal_ov5640_verify_jpeg(dev);
830}
831
832/* See the public header for the documented contract. */
834{
835 RA8_CHECK_NULL_PTR(dev, "ov5640", "jpeg_quality");
836 if (!dev->initialized) {
838 }
839 if (quant_scale > (uint8_t)k_ra8_ov5640_jpeg_quant_scale_max) {
841 }
845 quant_scale);
846}
847
866{
868 if (err == k_ra8_ok) {
870 }
871 if (err == k_ra8_ok) {
872 err = ra8_ov5640_read_reg(dev, (uint16_t)k_ov5640_reg_jpeg_length_lo, &raw->length_lo);
873 }
874 if (err == k_ra8_ok) {
875 err = ra8_ov5640_read_reg(dev, (uint16_t)k_ov5640_reg_jfifo_overflow, &raw->overflow);
876 }
877 if (err == k_ra8_ok) {
878 err = ra8_ov5640_read_reg(dev, (uint16_t)k_ov5640_reg_jpeg_ctrl00, &raw->jpeg_input);
879 }
880 if (err == k_ra8_ok) {
881 err = ra8_ov5640_read_reg(dev, (uint16_t)k_ov5640_reg_jpeg_ctrl01, &raw->jpeg_ctrl01);
882 }
883 if (err == k_ra8_ok) {
884 err = ra8_ov5640_read_reg(dev, (uint16_t)k_ov5640_reg_jpeg_ctrl04, &raw->jpeg_header);
885 }
886 return err;
887}
888
909{
911 if (err == k_ra8_ok) {
913 }
914 if (err == k_ra8_ok) {
916 }
917 if (err == k_ra8_ok) {
919 }
920 if (err == k_ra8_ok) {
922 }
923 if (err == k_ra8_ok) {
925 }
926 if (err == k_ra8_ok) {
928 }
929 if (err == k_ra8_ok) {
931 }
932 return err;
933}
934
935/* See the public header for the documented contract. */
937{
938 RA8_CHECK_NULL_PTR(dev, "ov5640", "jpeg_status");
939 RA8_CHECK_NULL_PTR(out_status, "ov5640", "jpeg_status");
940 *out_status = (ra8_ov5640_jpeg_status_t){};
941 if (!dev->initialized) {
943 }
945 const ra8_err_t err = internal_ov5640_read_jpeg_status(dev, &raw);
946 if (err != k_ra8_ok) {
947 return err;
948 }
949
950 *out_status = (ra8_ov5640_jpeg_status_t){
951 .encoded_bytes = ((uint32_t)raw.length_hi << (uint32_t)k_ov5640_jpeg_length_hi_shift) |
952 ((uint32_t)raw.length_mid << (uint32_t)k_ov5640_jpeg_length_mid_shift) |
953 (uint32_t)raw.length_lo,
954 .compression_width =
955 (uint16_t)(((uint16_t)raw.width_hi << (uint16_t)k_ov5640_dimension_hi_shift) | raw.width_lo),
956 .compression_height =
957 (uint16_t)(((uint16_t)raw.height_hi << (uint16_t)k_ov5640_dimension_hi_shift) |
958 raw.height_lo),
959 .jpeg_ctrl01 = raw.jpeg_ctrl01,
960 .vfifo_ctrl00 = raw.vfifo_ctrl00,
961 .href_minimum_blanking = raw.href_minimum,
962 .fifo_overflow = (raw.overflow & (uint8_t)k_ov5640_jfifo_overflow_mask) != 0U,
963 .input_is_yuv422 = (raw.jpeg_input & (uint8_t)k_ov5640_jpeg_input_yuv422_mask) != 0U,
964 .header_output = (raw.jpeg_header & (uint8_t)k_ov5640_jpeg_header_mask) != 0U,
965 .compression_enabled = (raw.timing_ctrl21 & (uint8_t)k_ov5640_jpeg_enable_mask) != 0U,
966 };
967 return k_ra8_ok;
968}
969
970/* See the public header for the documented contract. */
972{
973 if (dev == nullptr) {
974 return k_ra8_err_null_ptr;
975 }
976 if (!dev->initialized) {
978 }
979 const uint8_t value = enabled ? (uint8_t)k_ov5640_sw_reset_wake : (uint8_t)k_ov5640_sw_standby;
980 const ra8_err_t err = ra8_ov5640_write_reg(dev, (uint16_t)k_ov5640_reg_sw_reset, value);
981 if (err == k_ra8_ok) {
982 dev->bus.delay_ms(dev->bus.ctx, (uint32_t)k_ov5640_stream_settle_ms);
983 }
984 return err;
985}
Annotation-attribute framework macros for ra8-firmware.
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Validation and Error-Checking Macros for ra8-firmware.
#define RA8_CHECK_NULL_PTR(ptr, tag, message)
Reject nullptr pointer, returning k_ra8_err_null_ptr.
Definition ra8_check.h:243
Error Code Definitions for ra8-firmware.
@ k_ra8_err_not_supported
Requested feature not compiled in, not wired, or not supported by this MCU variant.
Definition ra8_err.h:180
@ k_ra8_err_invalid_arg
Invalid function argument.
Definition ra8_err.h:152
@ k_ra8_err_not_initialized
Module not initialized – _init() not yet called successfully.
Definition ra8_err.h:235
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
@ k_ra8_err_null_ptr
Pointer was NULL where a valid pointer was required.
Definition ra8_err.h:478
@ k_ra8_err_not_found
Requested item not found (lookup / search missed).
Definition ra8_err.h:173
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
ra8_err_t ra8_ov5640_read_reg(ra8_ov5640_t *dev, uint16_t reg, uint8_t *out_value)
Read one sensor register through the bound transport.
Definition ra8_ov5640.c:500
static ra8_err_t internal_ov5640_update_bits(ra8_ov5640_t *dev, uint16_t reg, uint8_t mask, uint8_t value)
Update selected bits in one sensor register.
Definition ra8_ov5640.c:538
static const ra8_ov5640_reg_write_t s_ov5640_vga_uyvy[]
OV5640 DVP init: PLL from 24 MHz XVCLK, VGA YUV422 live output.
Definition ra8_ov5640.c:201
ra8_ov5640_register_t
OV5640 SCCB register addresses + the expected chip-ID value.
Definition ra8_ov5640.c:33
@ k_ov5640_reg_vfifo_ctrl0b
VFIFO output control.
Definition ra8_ov5640.c:76
@ k_ov5640_reg_jpeg_ctrl04
JPEG header-output control.
Definition ra8_ov5640.c:63
@ k_ov5640_reg_jpeg_ctrl01
JPEG FIFO pacing control.
Definition ra8_ov5640.c:62
@ k_ov5640_reg_timing_y_end_lo
Sensor crop Y end low byte.
Definition ra8_ov5640.c:50
@ k_ov5640_reg_href_minimum
JPEG HREF minimum blanking.
Definition ra8_ov5640.c:80
@ k_ov5640_reg_pll_bypass
PLL bypass control.
Definition ra8_ov5640.c:44
@ k_ov5640_reg_jpeg_mode
DVP JPEG mode select.
Definition ra8_ov5640.c:78
@ k_ov5640_reg_isp_ctrl01
ISP feature-enable register.
Definition ra8_ov5640.c:82
@ k_ov5640_reg_timing_tc_reg20
Vertical timing and binning.
Definition ra8_ov5640.c:57
@ k_ov5640_reg_clock_select
System clock source.
Definition ra8_ov5640.c:45
@ k_ov5640_reg_jpeg_length_lo
JPEG length bits 7:0.
Definition ra8_ov5640.c:67
@ k_ov5640_reg_system_reset00
MCU reset controls.
Definition ra8_ov5640.c:34
@ k_ov5640_reg_clock_enable02
JPEG clock controls.
Definition ra8_ov5640.c:36
@ k_ov5640_reg_timing_y_start_hi
Sensor crop Y start high byte.
Definition ra8_ov5640.c:47
@ k_ov5640_reg_jpeg_quality
JPEG quantization scale.
Definition ra8_ov5640.c:64
@ k_ov5640_reg_clock_root
PCLK/SCLK root dividers.
Definition ra8_ov5640.c:46
@ k_ov5640_reg_compression_w_lo
Compressed-output width low.
Definition ra8_ov5640.c:73
@ k_ov5640_reg_chip_id_lo
Chip-ID low byte register.
Definition ra8_ov5640.c:39
@ k_ov5640_reg_format
DVP output pixel format register.
Definition ra8_ov5640.c:60
@ k_ov5640_reg_timing_y_offset_hi
Output Y offset high byte.
Definition ra8_ov5640.c:55
@ k_ov5640_reg_system_reset02
JPEG reset controls.
Definition ra8_ov5640.c:35
@ k_ov5640_reg_pll_multiplier
PLL multiplier.
Definition ra8_ov5640.c:42
@ k_ov5640_reg_pll_pre_div
PLL pre-divider.
Definition ra8_ov5640.c:43
@ k_ov5640_reg_vfifo_ctrl0c
VFIFO output control.
Definition ra8_ov5640.c:77
@ k_ov5640_reg_chip_id_hi
Chip-ID high byte register.
Definition ra8_ov5640.c:38
@ k_ov5640_reg_vfifo_ctrl00
VFIFO output control.
Definition ra8_ov5640.c:71
@ k_ov5640_reg_jpeg_ctrl1c
JPEG DVP control.
Definition ra8_ov5640.c:79
@ k_ov5640_reg_timing_vts_lo
Vertical total low byte.
Definition ra8_ov5640.c:54
@ k_ov5640_reg_jpeg_timing14
JPEG binning/orientation timing.
Definition ra8_ov5640.c:69
@ k_ov5640_reg_timing_tc_reg21
Timing/mirror and JPEG enable.
Definition ra8_ov5640.c:58
@ k_ov5640_reg_timing_y_start_lo
Sensor crop Y start low byte.
Definition ra8_ov5640.c:48
@ k_ov5640_reg_test
Pre-output test-pattern register.
Definition ra8_ov5640.c:84
@ k_ov5640_reg_pll_sys_div
PLL system-clock divider.
Definition ra8_ov5640.c:41
@ k_ov5640_reg_compression_w_hi
Compressed-output width high.
Definition ra8_ov5640.c:72
@ k_ov5640_reg_timing_hts_lo
Horizontal total low byte.
Definition ra8_ov5640.c:52
@ k_ov5640_reg_isp_mux
ISP output format-mux register.
Definition ra8_ov5640.c:83
@ k_ov5640_reg_timing_y_end_hi
Sensor crop Y end high byte.
Definition ra8_ov5640.c:49
@ k_ov5640_reg_jpeg_length_hi
JPEG length bits 23:16.
Definition ra8_ov5640.c:65
@ k_ov5640_reg_jpeg_ctrl00
JPEG input-format control.
Definition ra8_ov5640.c:61
@ k_ov5640_reg_jfifo_overflow
JPEG FIFO overflow status.
Definition ra8_ov5640.c:68
@ k_ov5640_reg_polarity_ctrl00
DVP clock and sync polarity.
Definition ra8_ov5640.c:81
@ k_ov5640_reg_timing_hts_hi
Horizontal total high byte.
Definition ra8_ov5640.c:51
@ k_ov5640_reg_jpeg_timing20
JPEG sampling timing.
Definition ra8_ov5640.c:70
@ k_ov5640_reg_sw_reset
System control register.
Definition ra8_ov5640.c:37
@ k_ov5640_reg_pll_bit_mode
PLL bit-mode control.
Definition ra8_ov5640.c:40
@ k_ov5640_reg_compression_h_lo
Compressed-output height low.
Definition ra8_ov5640.c:75
@ k_ov5640_reg_pclk_divider
DVP pixel-clock divider.
Definition ra8_ov5640.c:59
@ k_ov5640_reg_timing_vts_hi
Vertical total high byte.
Definition ra8_ov5640.c:53
@ k_ov5640_reg_jpeg_length_mid
JPEG length bits 15:8.
Definition ra8_ov5640.c:66
@ k_ov5640_reg_timing_y_offset_lo
Output Y offset low byte.
Definition ra8_ov5640.c:56
@ k_ov5640_reg_compression_h_hi
Compressed-output height high.
Definition ra8_ov5640.c:74
static ra8_err_t internal_ov5640_write_vga_base(ra8_ov5640_t *dev)
Program the board-qualified VGA base table.
Definition ra8_ov5640.c:651
static ra8_err_t internal_ov5640_configure_jpeg(ra8_ov5640_t *dev)
Apply the JPEG-specific overlay to the VGA base scene.
Definition ra8_ov5640.c:682
ra8_ov5640_delay_t
OV5640 settle delays around reset and register programming (ms).
Definition ra8_ov5640.c:150
@ k_ov5640_cfg_settle_ms
Settle after the register sequence.
Definition ra8_ov5640.c:154
@ k_ov5640_stream_settle_ms
Settle after standby/wake change.
Definition ra8_ov5640.c:153
@ k_ov5640_mcu_reset_ms
Settle after holding the MCU reset.
Definition ra8_ov5640.c:152
@ k_ov5640_reset_guard_ms
Guard before and after reset.
Definition ra8_ov5640.c:151
ra8_err_t ra8_ov5640_write_reg(ra8_ov5640_t *dev, uint16_t reg, uint8_t value)
Write one sensor register through the bound transport.
Definition ra8_ov5640.c:511
ra8_ov5640_value_t
OV5640 SCCB addressing, reset values, and byte-wrangling constants.
Definition ra8_ov5640.c:88
@ k_ov5640_timing_tc_reg20_jpeg
VGA JPEG vertical binning.
Definition ra8_ov5640.c:107
@ k_ov5640_jpeg_mode_mask
JPEG mode-select field.
Definition ra8_ov5640.c:98
@ k_ov5640_jpeg_sync_polarity_mask
JPEG VSYNC/HREF polarity bits.
Definition ra8_ov5640.c:99
@ k_ov5640_vfifo_ctrl0b_jpeg
JPEG VFIFO setting.
Definition ra8_ov5640.c:119
@ k_ov5640_mcu_reset_hold
Hold the internal MCU reset.
Definition ra8_ov5640.c:92
@ k_ov5640_jfifo_overflow_mask
JPEG FIFO overflow bit.
Definition ra8_ov5640.c:134
@ k_ov5640_pll_sys_div_raw
Qualified system divider.
Definition ra8_ov5640.c:122
@ k_ov5640_jpeg_y_end_hi
VGA crop Y end bits 15:8.
Definition ra8_ov5640.c:110
@ k_ov5640_pll_bypass_disabled
Use the programmed PLL.
Definition ra8_ov5640.c:125
@ k_ov5640_jpeg_sync_polarity
Align HREF pulses with high VD.
Definition ra8_ov5640.c:100
@ k_ov5640_byte_mask
Full-register readback mask.
Definition ra8_ov5640.c:94
@ k_ov5640_jpeg_quant_scale_mask
JPEG CTRL07 QS field.
Definition ra8_ov5640.c:131
@ k_ov5640_jpeg_reset_mask
JFIFO/SFIFO/JPEG reset bits.
Definition ra8_ov5640.c:130
@ k_ov5640_jpeg_hts_lo
VGA horizontal total bits 7:0.
Definition ra8_ov5640.c:113
@ k_ov5640_jpeg_timing14_vga
VGA binning/orientation timing.
Definition ra8_ov5640.c:105
@ k_ov5640_jpeg_input_yuv422_mask
JPEG CTRL00 input-format bit.
Definition ra8_ov5640.c:132
@ k_ov5640_jpeg_y_start_lo
VGA crop Y start bits 7:0.
Definition ra8_ov5640.c:109
@ k_ov5640_sw_reset_wake
Normal operation.
Definition ra8_ov5640.c:91
@ k_ov5640_jpeg_y_offset_lo
VGA Y offset bits 7:0.
Definition ra8_ov5640.c:117
@ k_ov5640_pll_pre_div_raw
Qualified PLL pre-divider.
Definition ra8_ov5640.c:124
@ k_ov5640_jpeg_clock_mask
JPEG and JPEG2x clock bits.
Definition ra8_ov5640.c:118
@ k_ov5640_jpeg_timing20_vga
VGA sampling timing.
Definition ra8_ov5640.c:106
@ k_ov5640_pclk_divider_raw
Qualified DVP PCLK divider.
Definition ra8_ov5640.c:128
@ k_ov5640_jpeg_enable_mask
0x3821 JPEG-enable bit.
Definition ra8_ov5640.c:129
@ k_ov5640_jpeg_mode_dvp_2
DVP compressed-frame mode 2.
Definition ra8_ov5640.c:97
@ k_ov5640_jpeg_vga_height_lo
VGA height bits 7:0.
Definition ra8_ov5640.c:139
@ k_ov5640_jpeg_vts_hi
VGA vertical total bits 15:8.
Definition ra8_ov5640.c:114
@ k_ov5640_jpeg_y_start_hi
VGA crop Y start bits 15:8.
Definition ra8_ov5640.c:108
@ k_ov5640_pll_bit_mode_raw
Qualified DVP PLL 8-bit mode.
Definition ra8_ov5640.c:121
@ k_ov5640_hi_byte_shift
Chip-ID high-byte shift.
Definition ra8_ov5640.c:93
@ k_ov5640_jpeg_ctrl00
YUV422 input and FIFO enable.
Definition ra8_ov5640.c:101
@ k_ov5640_pll_multiplier_raw
Qualified PLL multiplier.
Definition ra8_ov5640.c:123
@ k_ov5640_jpeg_vga_width_lo
VGA width bits 7:0.
Definition ra8_ov5640.c:137
@ k_ov5640_jpeg_ctrl1c
JPEG DVP control value.
Definition ra8_ov5640.c:104
@ k_ov5640_jpeg_ctrl04
Header and output control.
Definition ra8_ov5640.c:103
@ k_ov5640_isp_mux_yuv
Route YUV through ISP.
Definition ra8_ov5640.c:96
@ k_ov5640_clock_select_raw
Qualified PLL clock selection.
Definition ra8_ov5640.c:127
@ k_ov5640_jpeg_ctrl01
JPEG FIFO pacing control.
Definition ra8_ov5640.c:102
@ k_ov5640_vfifo_ctrl0c_jpeg
JPEG VFIFO setting.
Definition ra8_ov5640.c:120
@ k_ov5640_jpeg_hts_hi
VGA horizontal total bits 15:8.
Definition ra8_ov5640.c:112
@ k_ov5640_jpeg_header_mask
JPEG CTRL04 header-output bit.
Definition ra8_ov5640.c:133
@ k_ov5640_sw_reset_hold
Software reset (0x3008 bit 7).
Definition ra8_ov5640.c:89
@ k_ov5640_jpeg_vga_height_hi
VGA height bits 15:8.
Definition ra8_ov5640.c:138
@ k_ov5640_jpeg_vga_width_hi
VGA width bits 15:8.
Definition ra8_ov5640.c:136
@ k_ov5640_jpeg_y_offset_hi
VGA Y offset bits 15:8.
Definition ra8_ov5640.c:116
@ k_ov5640_isp_scale_enable_mask
ISP scaling-enable bit.
Definition ra8_ov5640.c:135
@ k_ov5640_jpeg_vts_lo
VGA vertical total bits 7:0.
Definition ra8_ov5640.c:115
@ k_ov5640_sw_standby
Software standby.
Definition ra8_ov5640.c:90
@ k_ov5640_clock_root_raw
Qualified clock-root dividers.
Definition ra8_ov5640.c:126
@ k_ov5640_jpeg_y_end_lo
VGA crop Y end bits 7:0.
Definition ra8_ov5640.c:111
@ k_ov5640_format_yuyv
YUYV/JPEG ISP input format.
Definition ra8_ov5640.c:95
ra8_ov5640_jpeg_length_shift_t
Bit positions used to combine the three JPEG length registers.
Definition ra8_ov5640.c:143
@ k_ov5640_jpeg_length_mid_shift
JPEG length middle-byte shift.
Definition ra8_ov5640.c:145
@ k_ov5640_jpeg_length_hi_shift
JPEG length high-byte shift.
Definition ra8_ov5640.c:144
@ k_ov5640_dimension_hi_shift
Compression dimension shift.
Definition ra8_ov5640.c:146
static ra8_err_t internal_ov5640_verify_jpeg(ra8_ov5640_t *dev)
Verify the JPEG-specific register scene.
Definition ra8_ov5640.c:769
ra8_err_t ra8_ov5640_stream_set(ra8_ov5640_t *dev, bool enabled)
Enter software standby or resume sensor streaming.
Definition ra8_ov5640.c:971
ra8_err_t ra8_ov5640_configure(ra8_ov5640_t *dev, ra8_ov5640_mode_t mode)
Software-reset and program one validated output mode.
Definition ra8_ov5640.c:801
ra8_err_t ra8_ov5640_jpeg_status_get(ra8_ov5640_t *dev, ra8_ov5640_jpeg_status_t *out_status)
Snapshot sensor JPEG length, overflow, and routing controls.
Definition ra8_ov5640.c:936
ra8_err_t ra8_ov5640_probe(ra8_ov5640_t *dev, uint16_t *out_id)
Probe both legal SCCB addresses and verify chip ID 0x5640.
Definition ra8_ov5640.c:612
static ra8_err_t internal_ov5640_read_chip_id(ra8_ov5640_t *dev, uint16_t *out_id)
Read and combine the OV5640 high and low chip-ID bytes.
Definition ra8_ov5640.c:597
ra8_err_t ra8_ov5640_init(ra8_ov5640_t *dev, const ra8_ov5640_bus_t *bus)
Bind a caller-supplied SCCB transport without touching the sensor.
Definition ra8_ov5640.c:484
static ra8_err_t internal_ov5640_verify(ra8_ov5640_t *dev, const ra8_ov5640_reg_expect_t *expected, uint32_t count)
Verify a bounded set of masked sensor register expectations.
Definition ra8_ov5640.c:567
ra8_err_t ra8_ov5640_set_jpeg_quantization_scale(ra8_ov5640_t *dev, uint8_t quant_scale)
Set the sensor JPEG encoder's raw quantization scale.
Definition ra8_ov5640.c:833
static ra8_err_t internal_ov5640_read_jpeg_status(ra8_ov5640_t *dev, ra8_ov5640_jpeg_status_raw_t *raw)
Read the register bytes comprising one JPEG status snapshot.
Definition ra8_ov5640.c:907
static ra8_err_t internal_ov5640_read_jpeg_status_format(ra8_ov5640_t *dev, ra8_ov5640_jpeg_status_raw_t *raw)
Read the JPEG length, FIFO, and format status registers.
Definition ra8_ov5640.c:865
static ra8_err_t internal_ov5640_verify_uyvy(ra8_ov5640_t *dev)
Verify the common UYVY register scene.
Definition ra8_ov5640.c:742
Transport-independent OmniVision OV5640 sensor driver.
@ k_ra8_ov5640_chip_id
Expected combined chip identifier.
Definition ra8_ov5640.h:31
ra8_ov5640_mode_t
Sensor output modes with validated register tables.
Definition ra8_ov5640.h:40
@ k_ra8_ov5640_mode_vga_jpeg
Sensor-encoded VGA JPEG stream.
Definition ra8_ov5640.h:42
@ k_ra8_ov5640_mode_vga_uyvy
Packed VGA UYVY DVP stream.
Definition ra8_ov5640.h:41
@ k_ra8_ov5640_jpeg_quant_scale_max
Lowest-quality raw scale.
Definition ra8_ov5640.h:49
@ k_ra8_ov5640_jpeg_quant_scale_default
Vendor reset-scale value.
Definition ra8_ov5640.h:48
@ k_ra8_ov5640_addr_primary
Default seven-bit SCCB address.
Definition ra8_ov5640.h:35
@ k_ra8_ov5640_addr_secondary
Alternate seven-bit SCCB address.
Definition ra8_ov5640.h:36
Injected SCCB and time services.
Definition ra8_ov5640.h:60
ra8_ov5640_write_fn_t write_reg
Injected single-register write.
Definition ra8_ov5640.h:62
ra8_ov5640_delay_fn_t delay_ms
Injected millisecond delay.
Definition ra8_ov5640.h:63
void * ctx
Caller-owned transport context.
Definition ra8_ov5640.h:64
ra8_ov5640_read_fn_t read_reg
Injected single-register read.
Definition ra8_ov5640.h:61
Raw register bytes used to assemble one JPEG status snapshot.
Definition ra8_ov5640.c:176
uint8_t overflow
JPEG FIFO status.
Definition ra8_ov5640.c:180
uint8_t height_hi
Compression height high.
Definition ra8_ov5640.c:187
uint8_t width_lo
Compression width low.
Definition ra8_ov5640.c:186
uint8_t href_minimum
Minimum HREF blanking.
Definition ra8_ov5640.c:189
uint8_t length_mid
Encoded length bits 15:8.
Definition ra8_ov5640.c:178
uint8_t height_lo
Compression height low.
Definition ra8_ov5640.c:188
uint8_t length_hi
Encoded length bits 23:16.
Definition ra8_ov5640.c:177
uint8_t jpeg_ctrl01
JPEG FIFO pacing.
Definition ra8_ov5640.c:182
uint8_t jpeg_input
JPEG input format.
Definition ra8_ov5640.c:181
uint8_t length_lo
Encoded length bits 7:0.
Definition ra8_ov5640.c:179
uint8_t jpeg_header
JPEG header control.
Definition ra8_ov5640.c:183
uint8_t timing_ctrl21
JPEG enable state.
Definition ra8_ov5640.c:190
uint8_t vfifo_ctrl00
VFIFO operating mode.
Definition ra8_ov5640.c:184
uint8_t width_hi
Compression width high.
Definition ra8_ov5640.c:185
Snapshot of the OV5640 JPEG pipeline and its most recent frame.
Definition ra8_ov5640.h:75
One masked OV5640 register readback expectation.
Definition ra8_ov5640.c:169
uint16_t reg
OV5640 register address.
Definition ra8_ov5640.c:170
uint8_t mask
Bits relevant to this mode.
Definition ra8_ov5640.c:171
uint8_t value
Expected masked value.
Definition ra8_ov5640.c:172
One OV5640 SCCB register write (16-bit address, 8-bit value).
Definition ra8_ov5640.c:163
uint16_t reg
OV5640 register address.
Definition ra8_ov5640.c:164
uint8_t val
Value to program.
Definition ra8_ov5640.c:165
Caller-owned sensor instance; supports multiple independent parts.
Definition ra8_ov5640.h:68
uint8_t address
Selected seven-bit SCCB address.
Definition ra8_ov5640.h:70
bool initialized
Successful binding marker.
Definition ra8_ov5640.h:71
ra8_ov5640_bus_t bus
Copied transport callbacks.
Definition ra8_ov5640.h:69