ra8_cac.c

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#include "ra8_cac.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_cac_regs.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
 
static const char* s_tag = "CAC";
 
typedef enum : uint8_t {
  k_ra8_cacr0_cfme  = 0U, 
  k_ra8_castr_ferrf = 0U, 
  k_ra8_castr_mendf = 1U, 
  k_ra8_castr_ovff  = 2U, 
} ra8_cac_bit_t;

typedef enum : uint32_t {
  k_ra8_cac_castr_to_caicr_shift = 4U,      
  k_ra8_cac_cfme_settle_iters    = 1024U,   
  k_ra8_cac_poll_limit           = 200000U, 
} ra8_cac_misc_t;

typedef enum : uint8_t {
  k_ra8_cac_status_mask_all = k_ra8_cac_status_mendf | k_ra8_cac_status_ovff |
                              k_ra8_cac_status_ferrf, 
} ra8_cac_bits_w43_t;

RA8_INTERNAL static inline void internal_cac_wait_cfme(volatile r_cac_regs_t* reg, uint8_t expect)
{
  for (uint32_t i = 0U; i < k_ra8_cac_cfme_settle_iters; i++) {
#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
    /* HUM Ch 10.2.1 "CACR0 : CAC Control Register 0" p 421 */
    const bool settled = ra8_fake_mmio_poll(&reg->CACR0, i, reg->CACR0 == expect);
#else
    /* HUM Ch 10.2.1 "CACR0 : CAC Control Register 0" p 421 */
    const bool settled = reg->CACR0 == expect;
#endif
    if (settled) {
      return;
    }
  }
}
 
ra8_err_t ra8_cac_init(uint16_t upper, uint16_t lower)
{
  /* HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C", p 446 */
  const ra8_err_t mst_err = ra8_mstp_enable(k_ra8_mstp_cac);
  RA8_RETURN_ON_ERROR(mst_err, s_tag, "cac_init: mstp enable");
 
  volatile r_cac_regs_t* reg = ra8_cac();
  /* HUM Ch 10.2.1 "CACR0 : CAC Control Register 0" p 421 -- CFME must be
   * cleared before CACR1/CACR2/limits are programmed (FSP r_cac.c
   * r_cac_hw_configure() does the same, then waits on CACR0 readback). */
  reg->CACR0 = 0U;
  internal_cac_wait_cfme(reg, 0U);
  /* HUM Ch 10.2.4 "CAICR" p 424 */ /* clear all stale W1C status flags. */
  reg->CAICR = (uint8_t)(k_ra8_cac_status_mask_all << (uint8_t)k_ra8_cac_castr_to_caicr_shift);
  /* HUM Ch 10.2.2 "CACR1 : CAC Control Register 1" p 422 */
  reg->CACR1 = 0U;
  /* HUM Ch 10.2.3 "CACR2 : CAC Control Register 2" p 423 */
  reg->CACR2 = 0U;
  /* HUM Ch 10.2.6 "CAULVR : CAC Upper Limit Value Register" p 426 */
  reg->CAULVR = upper;
  /* HUM Ch 10.2.7 "CALLVR : CAC Lower Limit Value Register" p 426 */
  reg->CALLVR = lower;
  ra8_log_info(s_tag, "cac_init");
  return k_ra8_ok;
}
 
ra8_err_t ra8_cac_measure(uint16_t* out_count)
{
  RA8_CHECK_NULL_PTR(out_count, s_tag, "out_count must not be nullptr");
  volatile r_cac_regs_t* reg = ra8_cac();
 
  /* HUM Ch 10.2.1 "CACR0 : CAC Control Register 0" p 421 -- CFME=1 starts
   * a measurement; CASTR.MENDF asserts when the window completes. FSP
   * r_cac.c R_CAC_StartMeasurement() reads CACR0 back to confirm CFME
   * propagation before relying on the result. */
  const uint8_t cfme_set = (uint8_t)(1U << k_ra8_cacr0_cfme);
  reg->CACR0             = cfme_set;
  internal_cac_wait_cfme(reg, cfme_set);
 
  for (uint32_t i = 0U; i < k_ra8_cac_poll_limit; i++) {
    /* HUM Ch 10.2.5 "CASTR : CAC Status Register" p 425 */
    if ((reg->CASTR & (uint8_t)(1U << k_ra8_castr_mendf)) != 0U) {
      /* HUM Ch 10.2.8 "CACNTBR : CAC Counter Buffer Register" p 426 */
      *out_count = reg->CACNTBR;
      reg->CACR0 = 0U;
      internal_cac_wait_cfme(reg, 0U);
      return k_ra8_ok;
    }
  }
  reg->CACR0 = 0U;
  internal_cac_wait_cfme(reg, 0U);
  return k_ra8_err_hw_timeout;
}
 
/* =============================================================================
 * full build-out
 * =============================================================================
 */

typedef struct {
  ra8_cac_event_fn_t fn;  
  void*              ctx; 
} ra8_cac_state_t;
 
static ra8_cac_state_t s_cac_state;
 
ra8_err_t ra8_cac_deinit(void)
{
  volatile r_cac_regs_t* reg = ra8_cac();
  /* HUM Ch 10.2.1 "CACR0" p 421 -- stop measurement; FSP R_CAC_Close()
   * confirms CFME cleared before powering down via MSTP. */
  reg->CACR0 = 0U;
  internal_cac_wait_cfme(reg, 0U);
  reg->CACR1      = 0U;
  reg->CACR2      = 0U;
  reg->CAICR      = 0U;
  s_cac_state.fn  = nullptr;
  s_cac_state.ctx = nullptr;
  return ra8_mstp_disable(k_ra8_mstp_cac);
}
 
ra8_err_t ra8_cac_get_status(uint8_t* out_mask)
{
  RA8_CHECK_NULL_PTR(out_mask, s_tag, "out_mask must not be nullptr");
  *out_mask = (uint8_t)(ra8_cac()->CASTR & k_ra8_cac_status_mask_all);
  return k_ra8_ok;
}
 
ra8_err_t ra8_cac_clear_status(uint8_t mask)
{
  volatile r_cac_regs_t* reg = ra8_cac();
  /* HUM Ch 10.2.4 "CAICR : CAC Interrupt Control Register" p 424 -- the
   * write-1-to-clear bits are FERRFCL=bit4, MENDFCL=bit5, OVFFCL=bit6,
   * which sit `k_ra8_cac_castr_to_caicr_shift` (= 4) bits above the
   * matching CASTR FERRF/MENDF/OVFF flags. Cross-verified against FSP
   * r_cac.c CAC_PRV_CAICR_FERRFCL_OFFSET=4 / MENDFCL=5 / OVFFCL=6. */
  const uint8_t castr_bits = (uint8_t)(mask & k_ra8_cac_status_mask_all);
  const uint8_t caicr_clr  = (uint8_t)(castr_bits << (uint8_t)k_ra8_cac_castr_to_caicr_shift);
  reg->CAICR               = caicr_clr;
  return k_ra8_ok;
}
 
ra8_err_t ra8_cac_attach_handler(ra8_cac_event_fn_t fn, void* ctx)
{
  s_cac_state.fn  = fn;
  s_cac_state.ctx = ctx;
  return k_ra8_ok;
}
 
void ra8_cac_dispatch(void)
{
  volatile r_cac_regs_t* reg  = ra8_cac();
  const uint8_t          mask = (uint8_t)(reg->CASTR & k_ra8_cac_status_mask_all);
  /* HUM Ch 10.2.4 "CAICR" p 424 -- write 1 to FERRFCL/MENDFCL/OVFFCL
   * (bits 4/5/6) to clear the matching CASTR flag, mirroring the FSP
   * ISR pattern `R_CAC->CAICR |= CAC_PRV_CAICR_*FCL_MASK`. */
  reg->CAICR                   = (uint8_t)(mask << (uint8_t)k_ra8_cac_castr_to_caicr_shift);
  const ra8_cac_event_fn_t fn  = s_cac_state.fn;
  void* const              ctx = s_cac_state.ctx;
  if (fn != nullptr) {
    fn(ctx, mask);
  }
}
 
ra8_err_t ra8_cac_enter_stop(void)
{
  volatile r_cac_regs_t* reg = ra8_cac();
  /* HUM Ch 10.2.1 "CACR0" p 421 */ /* stop measurement before MSTP gate. */
  reg->CACR0 = 0U;
  internal_cac_wait_cfme(reg, 0U);
  return ra8_mstp_disable(k_ra8_mstp_cac);
}
 
ra8_err_t ra8_cac_exit_stop(void)
{
  return ra8_mstp_enable(k_ra8_mstp_cac);
}