ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
Loading...
Searching...
No Matches
RA8D2 Hardware User's Manual – Chapter Map

Source document: docs/reference/ra8d2-hardware-user-manual.pdf (Rev. 1.30, Feb 2026)

Total PDF pages: 4291

This file is the page-range source of truth for HUM citations. Generated by scripts/gen/build_chapter_map.sh. Citations in source code use the form /* HUM Ch X.Y "section name", p NNNN */ and are validated by scripts/checks/cite_check.py against the page ranges below.

Page numbers below are PDF page numbers, which match the printed page numbers in this manual revision.

Chapters

Ch Title Start End
1 Overview 69 110
2 CPU 111 203
3 Inter-Processor Communication (IPC) 204 233
4 Operating Modes 234 235
5 Address Space 236 243
6 Resets 244 277
7 Option-Setting Memory 278 299
8 Programmable Voltage Detection (PVD) 300 316
9 Clock Generation Circuit 317 419
10 Clock Frequency Accuracy Measurement Circuit (CAC) 420 428
11 Low Power Mode 429 497
12 Battery Backup Function 498 519
13 Register Write Protection Function 520 523
14 Interrupt Controller Unit (ICU) 524 582
15 Buses 583 691
16 Memory Protection Unit (MPU) 692 728
17 DMA Controller (DMAC) 729 783
18 Data Transfer Controller (DTC) 784 816
19 Event Link Controller (ELC) 817 836
20 I/O Ports 837 870
21 Port Output Enable for GPT (POEG) 871 877
22 General PWM Timer (GPT) 878 1151
23 PWM Delay Generation Circuit (PDG) 1152 1163
24 Low Power Asynchronous General Purpose Timer (AGT) 1164 1186
25 Ultra-Low-Power Timer (ULPT) 1187 1218
26 Realtime Clock (RTC) 1219 1255
27 Watchdog Timer (WDT) 1256 1270
28 Independent Watchdog Timer (IWDT) 1271 1286
29 Layer 3 Ethernet Switch Module (ESWM) 1287 1320
30 Ethernet Message Forwarding Engine (MFWD) 1321 1589
31 Ethernet Common Agent (COMA) 1590 1626
32 Ethernet Agent (ETHA) 1627 1702
33 Ethernet MAC (RMAC) 1703 1786
34 Ethernet CPU Agent (GWCA) 1787 1924
35 Ethernet Generic PTP Timer (GPTP) 1925 1964
36 USB 2.0 Full-Speed Module (USBFS) 1965 2058
37 USB 2.0 High-Speed Module (USBHS) 2059 2173
38 Serial Communications Interface (SCI) 2174 2366
39 I2C Bus Interface (IIC) 2367 2444
40 I3C Bus Interface (I3C) 2445 2701
41 CAN with Flexible Data-rate (CANFD) 2702 2867
42 CANFD ECC (CNECC) 2868 2876
43 Serial Peripheral Interface (SPI) 2877 2985
44 Octal Serial Peripheral Interface (OSPI) 2986 3047
45 Decryption On The Fly (DOTF) 3048 3050
46 Serial Sound Interface Enhanced (SSIE) 3051 3121
47 SD/MMC Host Interface (SDHI) 3122 3179
48 Cyclic Redundancy Check (CRC) 3180 3189
49 Pulse Density Modulation Interface (PDM-IF) 3190 3256
50 Boundary Scan 3257 3262
51 Security Features 3263 3301
52 Renesas Secure IP (RSIP-E50D) 3302 3307
53 16-bit A/D Converter (ADC16H) 3308 3489
54 12-Bit D/A Converter (DAC12) 3490 3496
55 Temperature Sensor (TSN) 3497 3507
56 High-Speed Analog Comparator (ACMPHS) 3508 3517
57 Data Operation Circuit (DOC) 3518 3526
58 SRAM 3527 3541
59 MRAM 3542 3625
60 Capture Engine Unit (CEU) 3626 3682
61 Graphics Subsystem 3683 3684
62 2D Drawing Engine (DRW) 3685 3743
63 Graphics LCD Controller (GLCDC) 3744 3821
64 MIPI PHY 3822 3838
65 MIPI DSI 3839 3934
66 MIPI CSI Interface 3935 3972
67 Video Input Module (VIN) 3973 4031
68 Internal Voltage Regulator 4032 4034
69 Electrical Characteristics 4035 4291

Security / TrustZone reference index

The TrustZone partitioning work leans on the following HUM chapters. Each entry is hand-verified against the rendered TOC pages and the chapter body via the Read tool, not just pdftotext.

  • SAU / IDAU and Armv8-M security extension
    • Ch 2 "CPU", subsection 2.3 "Implementation Options" – declares Armv8-M Security Extension and the Cortex-M85 PMSAv8 / Secure MPU layout.
    • Ch 16 "Memory Protection Unit (MPU)" – Secure MPU (MPU_S) and Non-Secure MPU (MPU_NS) region rules; this is where system_init.c writes its SAU regions in tandem with the CPU's PMSAv8.
  • Per-peripheral security attribution registers
    • Ch 6 "Resets", register 6.2.1 RSTSAR (Reset Security Attribution Register).
    • Ch 8 "Programmable Voltage Detection (PVD)", register 8.2.1 PVDSAR.
    • Ch 9 "Clock Generation Circuit", register 9.2.1 CGFSAR (Clock Generation Function Security Attribute Register).
    • Ch 3 "Inter-Processor Communication (IPC)", registers 3.2.1 IPCSAR / 3.2.2 IPCPAR.
    • Each peripheral chapter (SCI, IIC, SPI, GPT, ADC, CRC, USB, ETH, GLCDC, ...) carries its own xxxSAR register near the head of its register description block; cite_check picks these up by chapter rather than by exhaustive listing.
  • Memory map and address-space partitioning
    • Ch 5 "Address Space", subsections 5.1 "Address Space", 5.2 "External Address Space", 5.3 "Peripheral I/O Register Address Space" – the canonical Secure / Non-Secure address split lives here.
    • Ch 15 "Buses" – bus initiator security attribution and the bus-side filters that back the per-peripheral SAR registers.
    • Ch 58 "SRAM" and Ch 59 "MRAM" – the Secure / Non-Secure halves of MRAM and the SRAM-0 / SRAM-1 split that the linker script consumes.
    • Ch 7 "Option-Setting Memory" – FSBL secure boot path, anti-rollback counters, OEM root-key hashes; the boot trust anchor for the Secure world.
  • NSC veneer placement
    • Ch 2 "CPU", subsection 2.3 "Implementation Options" and the Armv8-M security extension references therein – the SG / BXNS / BLXNS instruction set used by libs/ra8_nsc/'s veneers.
    • Ch 16 "Memory Protection Unit (MPU)" – the .gnu.sgstubs linker section must land in a region the Secure MPU marks as Secure-execute-only and Non-Secure-callable; wires this up.
  • Security feature overview (cross-cutting)
    • Ch 51 "Security Features" – top-level security feature index; pointer to RSIP, secure debug, lifecycle.
    • Ch 52 "Renesas Secure IP (RSIP-E50D)" – key vault, AES, SHA, TRNG – key_vault.c lives behind these.