35#include <unicorn/unicorn.h>
68bool emulate_mve(uc_engine* uc, uint32_t pc0,
const uint8_t code0[4]);
230typedef enum : uint32_t {
ELF32 image services for the board emulator (load / symbols / vectors).
bool emu_div0_fault_pending(void)
Whether a trapping divide-by-zero is latched for the run loop.
void div0_seam_install(const emu_elf_source_t *elf)
Scan the image for UDIV/SDIV sites so the div-0 trap can arm later.
void emu_insn_seams_install(uc_engine *uc)
Arm the invalid-instruction dispatcher on the engine.
void emu_div0_count_trap(void)
Count one synthesised divide-by-zero UsageFault (telemetry).
void div0_synth_usagefault(uc_engine *uc, uint32_t vtor_base)
Synthesise a UsageFault (#6) for a trapped divide-by-zero.
uint64_t emu_mve_emulated_count(void)
Count of MVE instructions emulated this run (run-end telemetry).
bool on_invalid_insn(uc_engine *uc, void *user)
UC_HOOK_INSN_INVALID dispatcher: service or report a trapped opcode.
void emu_div0_clear_fault(void)
Clear the latched divide-by-zero fault.
bool emu_mve_nocp_spurious(uint32_t pc)
Report whether an invalid-instruction trap at pc is the bogus one Unicorn raises just after the MVE s...
void long_shift_seam_install(uc_engine *uc, const emu_elf_source_t *elf)
Scan the loaded image and install a hook at every immediate long-shift.
bool emu_mve_nocp_emulate(uc_engine *uc, uint32_t pc)
Emulate an MVE contiguous load/store from the NoCP UsageFault.
void emu_div0_disarm(void)
Drop the armed state after a warm reboot re-loads the image.
div0_field_t
UDIV/SDIV decode masks + fault field bits for the div-0 seam.
@ k_div0_hw2_mask
hw2[15:12] and hw2[7:4] must be 1111.
@ k_div0_cfsr_divzero
CFSR.UFSR.DIVBYZERO (0x02000000).
@ k_div0_insn_len
UDIV/SDIV are 32-bit Thumb-2.
@ k_div0_udf_b0
UDF.W #0 little-endian byte 0.
@ k_div0_udf_b1
UDF.W #0 little-endian byte 1.
@ k_div0_hw1_udiv
UDIV T1: hw1[15:4] == 0xFBB.
@ k_div0_rd_shift
hw2[11:8] = Rd (destination register).
@ k_div0_hw1_sdiv
SDIV T1: hw1[15:4] == 0xFB9.
@ k_div0_reg_sp
r13 (SP): UNPREDICTABLE as UDIV d/n/m.
@ k_div0_int32_min
INT32_MIN: the SDIV / -1 overflow edge.
@ k_div0_hw1_mask
hw1[15:4] selects the divide opcode.
@ k_div0_reg_pc
r15 (PC): UNPREDICTABLE as UDIV d/n/m.
@ k_div0_reg_mask
4-bit register field (Rn / Rm / Rd).
@ k_div0_udf_b3
UDF.W #0 little-endian byte 3.
@ k_div0_hw2_fixed
Their required value for a real divide.
uint32_t emu_div0_fault_pc(void)
PC of the divide that latched the pending fault.
void fast_sd_seam_install(uc_engine *uc, const emu_elf_source_t *elf)
Install the --fast-sd block-read hook if opted-in and the symbol exists.
bool emulate_div0_patched(uc_engine *uc, uint32_t pc, const uint8_t code[4])
Service an undefined-instruction trap that landed on an armed divide.
void emu_fast_sd_enable(void)
Opt in to the –fast-sd block-serving seam for this run.
void div0_patch_sites(uc_engine *uc)
Overwrite every tracked divide with UDF so divide-by-zero can trap.
bool emulate_long_shift_reg(uc_engine *uc, uint32_t pc, const uint8_t code[4])
Emulate a register-form Armv8.1-M long shift (LSLL/ASRL) that trapped.
bool emu_mve_nocp_take(void)
Test and clear the "NoCP fault serviced by the MVE seam" latch.
bool emulate_mve(uc_engine *uc, uint32_t pc0, const uint8_t code0[4])
Emulate a run of consecutive auto-vectoriser MVE instructions.
uint64_t emu_lob_emulated_count(void)
Count of LOB (DLS/LE) instructions emulated this run (telemetry).
Annotation-attribute framework macros for ra8-firmware.
One independently owned immutable raw-descriptor ELF source.