board_periph_ulpt.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_periph_block.h"
#include "emu_host_io_internal.h"

typedef enum : uint32_t {
  k_ulpt_block_order = 64U, 
} ulpt_order_t;

typedef enum : uint64_t {
  k_ulpt_base   = 0x40220000UL,  
  k_ulpt_stride = 0x100UL,       
  k_ulpt_count  = 2UL,           
  k_ulpt_span   = 0x100UL * 2UL, 
} ulpt_geom_t;

typedef enum : uint64_t {
  k_ulpt_off_cnt = 0x00UL, 
  k_ulpt_off_cma = 0x04UL, 
  k_ulpt_off_cmb = 0x08UL, 
  k_ulpt_off_cr  = 0x0CUL, 
  k_ulpt_off_mr1 = 0x0DUL, 
  k_ulpt_off_mr2 = 0x0EUL, 
  k_ulpt_off_mr3 = 0x0FUL, 
  k_ulpt_off_ioc = 0x10UL, 
} ulpt_off_t;

typedef enum : uint8_t {
  k_ulpt_cr_tstart = 0x01U, 
  k_ulpt_cr_tcstf  = 0x02U, 
  k_ulpt_cr_tstop  = 0x04U, 
  k_ulpt_cr_tundf  = 0x20U, 
} ulpt_cr_bit_t;

typedef enum : uint32_t {
  k_ulpt_step_per_chunk =
    0x40000U, 
} ulpt_rate_t;

typedef enum : uint16_t {
  k_ulpt_event_ch0_underflow = 0x080U, 
} ulpt_event_t;

typedef enum : uint32_t {
  k_ulpt_byte_mask = 0xFFU, 
  k_ulpt_byte_bits = 8U,    
} ulpt_byte_t;

typedef struct {
  uint32_t counter;    
  uint32_t reload;     
  uint32_t cmpa;       
  uint32_t cmpb;       
  uint8_t  cr;         
  uint8_t  mr1;        
  uint8_t  mr2;        
  uint8_t  mr3;        
  uint8_t  ioc;        
  uint32_t underflows; 
} ulpt_channel_t;
 
static ulpt_channel_t s_ulpt[k_ulpt_count];
 
/* =============================================================================
 * Register-cell access (route a byte access to the addressed channel field).
 * =============================================================================
 */

RA8_INTERNAL static uint32_t internal_ulpt_cell_value(const ulpt_channel_t* c, uint64_t off)
{
  /* HUM Ch 25.2.6 "ULPT : ULPT Counter Register" p 1198 */
  if (off < (uint64_t)k_ulpt_off_cma) {
    return c->counter;
  }
  /* HUM Ch 25 "Ultra-Low-Power Timer (ULPT)" p 1187 -- ULPTCMA */
  if (off < (uint64_t)k_ulpt_off_cmb) {
    return c->cmpa;
  }
  /* HUM Ch 25 "Ultra-Low-Power Timer (ULPT)" p 1187 -- ULPTCMB */
  if (off < (uint64_t)k_ulpt_off_cr) {
    return c->cmpb;
  }
  /* HUM Ch 25.2.1 "ULPTCR : ULPT Control Register" p 1190 */
  if (off == (uint64_t)k_ulpt_off_cr) {
    return c->cr;
  }
  /* HUM Ch 25.2.2 "ULPTMR1 : ULPT Mode Register 1" p 1192 */
  if (off == (uint64_t)k_ulpt_off_mr1) {
    return c->mr1;
  }
  /* HUM Ch 25.2.3 "ULPTMR2 : ULPT Mode Register 2" p 1192 */
  if (off == (uint64_t)k_ulpt_off_mr2) {
    return c->mr2;
  }
  /* HUM Ch 25.2.4 "ULPTMR3 : ULPT Mode Register 3" p 1195 */
  if (off == (uint64_t)k_ulpt_off_mr3) {
    return c->mr3;
  }
  /* HUM Ch 25.2.5 "ULPTIOC : ULPT I/O Control Register" p 1195 */
  return c->ioc;
}

RA8_INTERNAL static uint64_t internal_ulpt_cell_base(uint64_t off)
{
  if (off < (uint64_t)k_ulpt_off_cma) {
    return (uint64_t)k_ulpt_off_cnt;
  }
  if (off < (uint64_t)k_ulpt_off_cmb) {
    return (uint64_t)k_ulpt_off_cma;
  }
  if (off < (uint64_t)k_ulpt_off_cr) {
    return (uint64_t)k_ulpt_off_cmb;
  }
  return off; /* the 8-bit control / mode / io cells are one byte each */
}
 
/* =============================================================================
 * MMIO read / write.
 * =============================================================================
 */

RA8_INTERNAL static uint64_t internal_ulpt_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  const uint64_t rel = addr - (uint64_t)k_ulpt_base;
  const uint32_t ch  = (uint32_t)(rel / (uint64_t)k_ulpt_stride);
  if (ch >= (uint32_t)k_ulpt_count) {
    return 0U;
  }
  const uint64_t off  = rel % (uint64_t)k_ulpt_stride;
  const uint32_t cell = internal_ulpt_cell_value(&s_ulpt[ch], off);
  const uint32_t lane = (uint32_t)(off - internal_ulpt_cell_base(off));
  uint64_t       v    = 0U;
  for (unsigned i = 0U; i < size; i++) {
    const uint32_t b = lane + (uint32_t)i;
    if (b < (uint32_t)sizeof(uint32_t)) {
      const uint32_t lane_byte =
        (cell >> ((uint32_t)k_ulpt_byte_bits * b)) & (uint32_t)k_ulpt_byte_mask;
      v |= (uint64_t)lane_byte << ((uint32_t)k_ulpt_byte_bits * (uint32_t)i);
    }
  }
  return v;
}

RA8_INTERNAL static void internal_ulpt_write_cr(ulpt_channel_t* c, uint8_t value)
{
  /* HUM Ch 25.2.1 "ULPTCR : ULPT Control Register" p 1190 -- TUNDF is
   * write-0-to-clear (ra8_ulpt_stop clears it by writing 0); TSTART is RW and
   * TCSTF tracks TSTART. Mirrors the AGT AGTCR model. */
  const uint8_t status_keep = (uint8_t)(c->cr & value & (uint8_t)k_ulpt_cr_tundf);
  const uint8_t start       = (uint8_t)(value & (uint8_t)k_ulpt_cr_tstart);
  c->cr = (uint8_t)(start | (start != 0U ? (uint8_t)k_ulpt_cr_tcstf : 0U) | status_keep);
}

RA8_INTERNAL static void
internal_ulpt_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  const uint64_t rel = addr - (uint64_t)k_ulpt_base;
  const uint32_t ch  = (uint32_t)(rel / (uint64_t)k_ulpt_stride);
  if (ch >= (uint32_t)k_ulpt_count) {
    return;
  }
  ulpt_channel_t* c   = &s_ulpt[ch];
  const uint64_t  off = rel % (uint64_t)k_ulpt_stride;
  /* The ra8_ulpt driver only ever issues aligned, full-width stores: a 32-bit
   * write to ULPTCNT/CMA/CMB and an 8-bit write to ULPTCR/MRn/IOC. */
  if (off < (uint64_t)k_ulpt_off_cma) {
    /* HUM Ch 25.2.6 "ULPT : ULPT Counter Register" p 1198 -- a write seeds both
     * the live counter and the reload value (ra8_ulpt_start writes the period). */
    c->counter = (uint32_t)value;
    c->reload  = (uint32_t)value;
  } else if (off < (uint64_t)k_ulpt_off_cmb) {
    /* HUM Ch 25 "Ultra-Low-Power Timer (ULPT)" p 1187 -- ULPTCMA */
    c->cmpa = (uint32_t)value;
  } else if (off < (uint64_t)k_ulpt_off_cr) {
    /* HUM Ch 25 "Ultra-Low-Power Timer (ULPT)" p 1187 -- ULPTCMB */
    c->cmpb = (uint32_t)value;
  } else if (off == (uint64_t)k_ulpt_off_cr) {
    internal_ulpt_write_cr(c, (uint8_t)value);
  } else if (off == (uint64_t)k_ulpt_off_mr1) {
    /* HUM Ch 25.2.2 "ULPTMR1 : ULPT Mode Register 1" p 1192 */
    c->mr1 = (uint8_t)value;
  } else if (off == (uint64_t)k_ulpt_off_mr2) {
    /* HUM Ch 25.2.3 "ULPTMR2 : ULPT Mode Register 2" p 1192 */
    c->mr2 = (uint8_t)value;
  } else if (off == (uint64_t)k_ulpt_off_mr3) {
    /* HUM Ch 25.2.4 "ULPTMR3 : ULPT Mode Register 3" p 1195 */
    c->mr3 = (uint8_t)value;
  } else if (off == (uint64_t)k_ulpt_off_ioc) {
    /* HUM Ch 25.2.5 "ULPTIOC : ULPT I/O Control Register" p 1195 */
    c->ioc = (uint8_t)value;
  }
  (void)size;
}
 
/* =============================================================================
 * Per-tick down-count + edge-triggered underflow event.
 * =============================================================================
 */

RA8_INTERNAL static void internal_ulpt_tick_channel(uc_engine* uc, uint32_t ch)
{
  ulpt_channel_t* c = &s_ulpt[ch];
  /* HUM Ch 25.2.1 "ULPTCR : ULPT Control Register" p 1190 -- TSTART gate */
  if ((c->cr & (uint8_t)k_ulpt_cr_tstart) == 0U) {
    return; /* stopped: counter holds */
  }
  const uint32_t step = (uint32_t)k_ulpt_step_per_chunk;
  if (c->counter > step) {
    c->counter -= step;
    return;
  }
  /* Underflow: reload from the latched period and continue (periodic). */
  const uint32_t span    = c->reload + 1U;
  const uint32_t deficit = step - c->counter;
  c->counter             = c->reload - ((deficit - 1U) % span);
  /* Raise only on the rising edge of TUNDF -- one wake per armed period, until
   * the firmware clears it by stopping/re-arming the channel. */
  if ((c->cr & (uint8_t)k_ulpt_cr_tundf) == 0U) {
    /* HUM Ch 25.2.1 "ULPTCR : ULPT Control Register" p 1190 -- TUNDF set */
    c->cr |= (uint8_t)k_ulpt_cr_tundf;
    c->underflows++;
    if (ch == 0U) {
      board_periph_icu_raise_event(uc, (uint16_t)k_ulpt_event_ch0_underflow);
    }
    if (board_periph_trace()) {
      (void)priv_emu_io_errf("  ULPT%u         : underflow (reload=0x%08X)\n", ch, c->reload);
    }
  }
}

RA8_INTERNAL static void internal_ulpt_tick(uc_engine* uc)
{
  for (uint32_t ch = 0U; ch < (uint32_t)k_ulpt_count; ch++) {
    internal_ulpt_tick_channel(uc, ch);
  }
}
 
/* =============================================================================
 * Reset / report.
 * =============================================================================
 */

RA8_INTERNAL static void internal_ulpt_reset(void)
{
  for (uint32_t ch = 0U; ch < (uint32_t)k_ulpt_count; ch++) {
    s_ulpt[ch] = (ulpt_channel_t){};
  }
}

RA8_INTERNAL static void internal_ulpt_report(void)
{
  for (uint32_t ch = 0U; ch < (uint32_t)k_ulpt_count; ch++) {
    const ulpt_channel_t* c = &s_ulpt[ch];
    if (c->underflows == 0U) {
      continue;
    }
    (void)priv_emu_io_errf("  ULPT%u         : counter=0x%08X underflows=%u (running=%s)\n",
                           ch,
                           c->counter,
                           c->underflows,
                           (c->cr & (uint8_t)k_ulpt_cr_tstart) ? "yes" : "no");
  }
}

static const board_periph_block_t s_k_ulpt_block = {
  .base   = (uint64_t)k_ulpt_base,
  .span   = (uint64_t)k_ulpt_span,
  .order  = (uint32_t)k_ulpt_block_order,
  .read   = internal_ulpt_read,
  .write  = internal_ulpt_write,
  .tick   = internal_ulpt_tick,
  .reset  = internal_ulpt_reset,
  .report = internal_ulpt_report,
  .name   = "ULPT",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_board_periph_ulpt_register(void)
{
  board_periph_register_block(&s_k_ulpt_block);
}