board_periph_reset.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_periph_block.h"
#include "emu_host_io_internal.h"

typedef enum : uint64_t {
  k_rstsr1_base = 0x4001E0C0UL, 
  k_rstsr1_span = 0x04UL,       
} reset1_geom_t;

typedef enum : uint64_t {
  k_rstsr0_base   = 0x4001EA40UL, 
  k_rstsr0_span   = 0x0CUL,       
  k_rstsr0_off_r0 = 0x00UL,       
  k_rstsr0_off_r2 = 0x04UL,       
  k_rstsr0_off_r3 = 0x08UL,       
} reset0_geom_t;

typedef enum : uint32_t {
  k_rstsr0_porf   = 0x01U,       
  k_rstsr1_iwdtrf = 0x00000001U, 
  k_rstsr1_wdtrf  = 0x00000002U, 
  k_rstsr1_swrf   = 0x00000004U, 
} reset_flag_t;

typedef enum : uint32_t {
  k_reset_block_order = 178U, 
} reset_order_t;

static uint32_t s_rstsr1; 
static uint8_t  s_rstsr0; 
static uint8_t  s_rstsr2; 
static uint8_t  s_rstsr3; 
 
/* A pending warm-reboot request raised by a peripheral model (e.g. the WDT on a
 * watchdog-reset underflow). The run loop polls board_periph_reset_take_request
 * each chunk and performs the reboot. 0 = none; otherwise the cause to latch. */
static uint32_t s_reboot_req_cause;

typedef enum : uint32_t {
  k_reboot_cause_none = 0U, 
  k_reboot_cause_wdt  = 1U, 
  k_reboot_cause_iwdt = 2U, 
} reboot_cause_t;
 
void board_periph_reset_request_reboot(bool watchdog, bool iwdt)
{
  if (watchdog) {
    s_reboot_req_cause = (uint32_t)k_reboot_cause_wdt;
  } else if (iwdt) {
    s_reboot_req_cause = (uint32_t)k_reboot_cause_iwdt;
  }
}
 
bool board_periph_reset_take_request(bool* out_watchdog, bool* out_iwdt)
{
  if ((out_watchdog == nullptr) || (out_iwdt == nullptr)) {
    return false;
  }
  if (s_reboot_req_cause == (uint32_t)k_reboot_cause_none) {
    return false;
  }
  *out_watchdog      = (s_reboot_req_cause == (uint32_t)k_reboot_cause_wdt);
  *out_iwdt          = (s_reboot_req_cause == (uint32_t)k_reboot_cause_iwdt);
  s_reboot_req_cause = (uint32_t)k_reboot_cause_none;
  return true;
}
 
void board_periph_reset_set_cause(bool power_on, bool software, bool watchdog, bool iwdt)
{
  if (power_on) {
    /* A power-on / cold reboot: PORF is the cause; leave it set (the reset model
     * retains it across the warm reboot) and assert nothing else. */
    s_rstsr0 |= (uint8_t)k_rstsr0_porf;
    return;
  }
  /* Any non-power-on reset clears PORF and latches the specific cause flag(s). */
  s_rstsr0 &= (uint8_t)~(uint8_t)k_rstsr0_porf;
  if (software) {
    s_rstsr1 |= (uint32_t)k_rstsr1_swrf;
  }
  if (watchdog) {
    s_rstsr1 |= (uint32_t)k_rstsr1_wdtrf;
  }
  if (iwdt) {
    s_rstsr1 |= (uint32_t)k_rstsr1_iwdtrf;
  }
}

RA8_INTERNAL static void internal_reset_reset(void)
{
  /* Intentionally a no-op: the RSTSRn flags must survive a warm reboot so the
   * firmware can read the cause that triggered it. They clear only at process
   * start (static init) where the constructor seeds PORF. */
}

RA8_INTERNAL static uint64_t internal_reset1_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)addr;
  (void)size;
  return s_rstsr1;
}

RA8_INTERNAL static void
internal_reset1_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  (void)addr;
  (void)size;
  /* Keep only bits that are set AND written as 1; a written 0 clears the bit. */
  s_rstsr1 &= (uint32_t)value;
}

RA8_INTERNAL static uint64_t internal_reset0_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  const uint64_t off = addr - (uint64_t)k_rstsr0_base;
  if (off == (uint64_t)k_rstsr0_off_r0) {
    return s_rstsr0;
  }
  if (off == (uint64_t)k_rstsr0_off_r2) {
    return s_rstsr2;
  }
  if (off == (uint64_t)k_rstsr0_off_r3) {
    return s_rstsr3;
  }
  return 0U;
}

RA8_INTERNAL static void
internal_reset0_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  (void)size;
  const uint64_t off = addr - (uint64_t)k_rstsr0_base;
  if (off == (uint64_t)k_rstsr0_off_r0) {
    s_rstsr0 &= (uint8_t)value; /* write-0-to-clear */
  } else if (off == (uint64_t)k_rstsr0_off_r2) {
    s_rstsr2 = (uint8_t)value; /* RSTSR2.CWSF is write-1 set; shadow it */
  } else if (off == (uint64_t)k_rstsr0_off_r3) {
    s_rstsr3 = (uint8_t)value;
  }
}

RA8_INTERNAL static void internal_reset_report(void)
{
  if ((s_rstsr1 == 0U) && ((s_rstsr0 & (uint8_t)k_rstsr0_porf) == 0U)) {
    return; /* nothing notable to report */
  }
  (void)priv_emu_io_errf("  RESET-CAUSE   : RSTSR0=0x%02X RSTSR1=0x%08X (%s%s%s%s)\n",
                         (unsigned)s_rstsr0,
                         s_rstsr1,
                         ((s_rstsr0 & (uint8_t)k_rstsr0_porf) != 0U) ? "POR " : "",
                         ((s_rstsr1 & (uint32_t)k_rstsr1_swrf) != 0U) ? "SW " : "",
                         ((s_rstsr1 & (uint32_t)k_rstsr1_wdtrf) != 0U) ? "WDT " : "",
                         ((s_rstsr1 & (uint32_t)k_rstsr1_iwdtrf) != 0U) ? "IWDT " : "");
}

static const board_periph_block_t s_k_reset1_block = {
  .base   = (uint64_t)k_rstsr1_base,
  .span   = (uint64_t)k_rstsr1_span,
  .order  = (uint32_t)k_reset_block_order,
  .read   = internal_reset1_read,
  .write  = internal_reset1_write,
  .tick   = nullptr,
  .reset  = internal_reset_reset,
  .report = internal_reset_report,
  .name   = "RESET-RSTSR1",
};

static const board_periph_block_t s_k_reset0_block = {
  .base   = (uint64_t)k_rstsr0_base,
  .span   = (uint64_t)k_rstsr0_span,
  .order  = (uint32_t)k_reset_block_order,
  .read   = internal_reset0_read,
  .write  = internal_reset0_write,
  .tick   = nullptr,
  .reset  = nullptr,
  .report = nullptr,
  .name   = "RESET-RSTSR0",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_reset_block_register(void)
{
  s_rstsr0 |= (uint8_t)k_rstsr0_porf; /* first-ever boot is a power-on reset */
  board_periph_register_block(&s_k_reset1_block);
  board_periph_register_block(&s_k_reset0_block);
}